View LT1886_322810.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT1886 Dual 700MHz, 200mA Operational Amplifier
FEATURES
s s s s s s s s s s s s s s s
DESCRIPTIO
700MHz Gain Bandwidth 200mA Minimum IOUT Low Distortion: -72dBc at 1MHz, 4VP-P, 25, AV = 2 Stable in AV 10, Simple Compensation for AV < 10 4.3V Minimum Output Swing, VS = 6V, RL = 25 7mA Supply Current per Amplifier 200V/s Slew Rate Stable with 1000pF Load 6nV/Hz Input Noise Voltage 2pA/Hz Input Noise Current 4mV Maximum Input Offset Voltage 4A Maximum Input Bias Current 400nA Maximum Input Offset Current 4.5V Minimum Input CMR, VS = 6V Specified at 6V, 2.5V
The LT(R)1886 is a 200mA minimum output current dual op amp with outstanding distortion performance. The amplifiers are gain-of-ten stable, but can be easily compensated for lower gains. The LT1886 features balanced, high impedance inputs with 4A maximum input bias current, and 4mV maximum input offset voltage. Single supply applications are easy to implement and have lower total noise than current feedback amplifier implementations. The output drives a 25 load to 4.3V with 6V supplies. On 2.5V supplies the output swings 1.5V with a 100 load. The amplifier is stable with a 1000pF capacitive load which makes it useful in buffer and cable driver applications. The LT1886 is manufactured on Linear Technology's advanced low voltage complementary bipolar process and is available in a thermally enhanced SO-8 package.
APPLICATIO S
s s s s
DSL Modems xDSL PCI Cards USB Modems Line Drivers
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
Single 12V Supply ADSL Modem Line Driver
12V 0.1F IN +
+
1/2 LT1886
12.4
HARMONIC DISTORTION (dBc)
-
909 10k 20k 100 1:2*
100 1F 10k 20k 1F 100 909 *COILCRAFT X8390-A OR EQUIVALENT
1886 TA01
12.4
0.1F IN -
1/2 LT1886
U
ADSL Modem Line Driver Distortion
-60 VS = 12V AV = 10 f = 200kHz 100 LINE 1:2 TRANSFORMER HD2 -80 -70 -90 HD3 -100 0 2 4 6 8 10 12 LINE VOLTAGE (VP-P) 14 16
1886 TA01a
U
+
-
U
1
LT1886
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW OUT A 1 -IN A 2 +IN A 3 V- 4 B 5 +IN B A 8 7 6 V+ OUT B -IN B
Total Supply Voltage (V + to V -) ........................... 13.2V Input Current (Note 2) ....................................... 10mA Input Voltage (Note 2) ............................................ VS Maximum Continuous Output Current (Note 3) DC ............................................................... 100mA AC ............................................................... 300mA Operating Temperature Range (Note 10) - 40C to 85C Specified Temperature Range (Note 9) .. - 40C to 85C Maximum Junction Temperature ......................... 150C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LT1886CS8 S8 PART MARKING 1886
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 80C/W (Note 4)
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VOS PARAMETER Input Offset Voltage Input Offset Voltage Drift IOS IB en in RIN CIN Input Offset Current (Note 5)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 6V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9)
CONDITIONS
q
MIN
TYP 1
MAX 4 5 17 400 600 4 6
UNITS mV mV V/C nA nA A A nV/Hz pA/Hz M k pF V V dB V dB dB V/mV V/mV V/mV V/mV V V V V V V mA mA
(Note 8)
q q
3 150 1.5
Input Bias Current
q
Input Noise Voltage Input Noise Current Input Resistance Input Capacitance Input Voltage Range (Positive) Input Voltage Range (Negative)
f = 10kHz f = 10kHz VCM = 4.5V Differential
q q
6 2 5 10 35 2 4.5 77 80 78 5.0 4.5 4.5 4.0 4.85 4.70 4.30 4.10 4.30 4.10 5.9 -5.2 98 2 86 12 12 5 4.6 4.5 800 500 -4.5
CMRR PSRR AVOL
Common Mode Rejection Ratio Minimum Supply Voltage Power Supply Rejection Ratio Large-Signal Voltage Gain
VCM = 4.5V Guaranteed by PSRR VS = 2V to 6.5V
q q q
VOUT = 4V, RL = 100
q
VOUT = 4V, RL = 25
q
VOUT
Output Swing
RL = 100, 10mV Overdrive
q
RL = 25, 10mV Overdrive
q
IOUT = 200mA, 10mV Overdrive
q
ISC
Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking)
(Note 3)
2
U
W
U
U
WW
W
LT1886
ELECTRICAL CHARACTERISTICS
SYMBOL SR PARAMETER Slew Rate Full Power Bandwidth GBW tr, tf Gain Bandwidth Rise Time, Fall Time Overshoot Propagation Delay tS Settling Time Harmonic Distortion IMD ROUT Intermodulation Distortion Output Resistance Channel Separation IS Supply Current
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 6V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9)
CONDITIONS AV = -10 (Note 6)
q
MIN 133 110
TYP 200 8 700 4 1 2.5 50 - 75/- 63 - 85/- 71 - 81/- 80 0.1
MAX
UNITS V/s V/s MHz MHz ns % ns ns dBc dBc dBc dB dB
4V Peak (Note 7) f = 1MHz AV = 10, 10% to 90% of 0.1V, RL = 100 AV = 10, 0.1V, RL = 100 AV = 10, 50% VIN to 50% VOUT, 0.1V, RL = 100 6V Step, 0.1% HD2, AV = 10, 2VP-P, f = 1MHz, RL = 100/25 HD3, AV = 10, 2VP-P, f = 1MHz, RL = 100/25 AV = 10, f = 0.9MHz, 1MHz, 14dBm, RL = 100/25 AV = 10, f = 1MHz VOUT = 4V, RL = 25
q
82 80
92 7 8.25 8.50
Per Amplifier
q
mA mA
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 2.5V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9)
SYMBOL VOS PARAMETER Input Offset Voltage Input Offset Voltage Drift IOS IB en in RIN CIN Input Offset Current
q
CONDITIONS (Note 5)
q
MIN
TYP 1.5
MAX 5 6 17 350 550 3.5 5.5
UNITS mV mV V/C nA nA A A nV/Hz pA/Hz M k pF V V dB V/mV V/mV V/mV V/mV V V V V V V
(Note 8)
q
5 100 1.2
Input Bias Current
q
Input Noise Voltage Input Noise Current Input Resistance Input Capacitance Input Voltage Range (Positive) Input Voltage Range (Negative)
f = 10kHz f = 10kHz VCM = 1V Differential
q q
6 2 10 20 50 2 1 75 5.0 4.5 4.5 4.0 1.50 1.40 1.35 1.25 0.87 0.80 2.4 -1.7 91 10 10 1.65 1.50 1 -1
CMRR AVOL
Common Mode Rejection Ratio Large-Signal Voltage Gain
VCM = 1V VOUT = 1V, RL = 100
q q
VOUT = 1V, RL = 25
q
VOUT
Output Swing
RL = 100, 10mV Overdrive
q
RL = 25, 10mV Overdrive
q
IOUT = 200mA, 10mV Overdrive
q
3
LT1886
ELECTRICAL CHARACTERISTICS
SYMBOL ISC SR PARAMETER Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) Slew Rate Full Power Bandwidth GBW tr, tf Gain Bandwidth Rise Time, Fall Time Overshoot Propagation Delay Harmonic Distortion IMD ROUT Intermodulation Distortion Output Resistance Channel Separation IS Supply Current (Note 3)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 2.5V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9)
CONDITIONS MIN TYP 600 400
q
MAX
UNITS mA mA V/s V/s MHz MHz ns % ns dBc dBc dBc dB dB
AV = -10 (Note 6) 1V Peak (Note 7) f = 1MHz AV = 10, 10% to 90% of 0.1V, RL = 100 AV = 10, 0.1V, RL = 100 AV = 10, 50% VIN to 50% VOUT, 0.1V, RL = 100 HD2, AV = 10, 2VP-P, f = 1MHz, RL = 100/25 HD3, AV = 10, 2VP-P, f = 1MHz, RL = 100/25 AV = 10, f = 0.9MHz, 1MHz, 5dBm, RL = 100/25 AV = 10, f = 1MHz VOUT = 1V, RL = 25
q
66 60
100 16 530 7 5 5 - 75/- 64 - 80/- 66 - 77/- 85 0.2
82 80
92 5 5.75 6.25
Per Amplifier
q
mA mA
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes. If the differential input voltage exceeds 0.7V, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to the device. JA is specified for a 2500mm2 test board covered with 2 oz copper on both sides. Note 5: Input offset voltage is exclusive of warm-up drift.
Note 6: Slew rate is measured between 2V on a 4V output with 6V supplies, and between 1V on a 1.5V output with 2.5V supplies. Note 7: Full power bandwidth is calculated from the slew rate: FPBW = SR/2VP. Note 8: This parameter is not 100% tested. Note 9: The LT1886C is guaranteed to meet specified performance from 0C to 70C. The LT1886C is designed, characterized and expected to meet specified performance from -40C to 85C but is not tested or QA sampled at these temperatures. For guaranteed I-grade parts, consult the factory. Note 10: The LT1886C is guaranteed functional over the operating temperature range of -40C to 85C.
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Temperature
15 VS = 6V
COMMON MODE RANGE (V)
10 VS = 2.5V
-0.2 -0.3 1.5 1.0 0.5 TA = 25C VOS > 1mV
INPUT BIAS CURRENT (A)
SUPPLY CURRENT (mA)
5
0 -50
-25
0 25 50 75 TEMPERATURE (C)
4
UW
100
1886 G01
Input Common Mode Range vs Supply Voltage
V+ -0.1
3.0 2.5 2.0 1.5 1.0 0.5 0
Input Bias Current vs Input Common Mode Voltage
TA = 25C IB = (IB + + IB -)/2
VS = 6V VS = 2.5V
V-
125
0
2
4 6 8 10 12 TOTAL SUPPLY VOLTAGE (V)
14
-6
-4 -2 0 2 4 INPUT COMMON MODE VOLTAGE (V)
6
1886 G02
1886 G03
LT1886 TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Temperature
3.5 IB = (IB + + IB -)/2
INPUT VOLTAGE NOISE (nV/Hz)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
3.0 INPUT BIAS CURRENT (A) 2.5 2.0 1.5 1.0 0.5 0 -50 VS = 6V
VS = 2.5V
-25
0 25 50 75 TEMPERATURE (C)
Output Saturation Voltage vs Temperature, VS = 6V
V
+
OUTPUT SATURATION VOLTAGE (V)
-0.5 -1.0 -1.5 1.5 1.0 IL = 150mA IL = 150mA
OUTPUT SATURATION VOLTAGE (V)
RL = 100 IL = 200mA IL = 200mA
OUTPUT STEP (V)
RL = 100 0.5 V- -50
-25
0 25 50 75 TEMPERATURE (C)
Gain and Phase vs Frequency
80 70 60 50 GAIN (dB) 40 30 20 10 0 -10 -20 1M 10M 100M FREQUENCY (Hz) TA = 25C AV = -10 RL = 100 VS = 2.5V GAIN PHASE VS = 2.5V VS = 6V VS = 6V 100 80 GAIN BANDWIDTH (MHz) 60 40 PHASE (DEG) 20 0 -20 -40 -60 -80 -100 1G
1886 G10
OUTPUT IMPEDANCE ()
UW
100
1886 G04
Input Noise Spectral Density
100 TA = 25C AV = 101 100
INPUT CURRENT NOISE (pA/Hz)
Output Short-Circuit Current vs Temperature
1000 900 800 700 600 500 400 300 200 100 0 -50 VIN = 0.2V -25 0 25 50 75 TEMPERATURE (C) 100 125 SOURCE, VS = 2.5V SINK, VS = 6V SINK, VS = 2.5V SOURCE, VS = 6V
10 en in
10
125
1 10
100
1k 10k FREQUENCY (Hz)
1 100k
1886 G05
1886 G06
Output Saturation Voltage vs Temperature, VS = 2.5V
V
+
Settling Time vs Output Step
6 VS = 6V
-0.5 -1.0 -1.5 1.5 1.0 0.5 V- -50 IL = 150mA IL = 150mA
RL = 100
4 10mV 1mV 2 0 -2 -4 10mV -6
100 125
IL = 200mA IL = 200mA
RL = 100
1mV 50 60
1886 G09
100
125
-25
0 25 50 75 TEMPERATURE (C)
0
10
20 30 40 SETTLING TIME (ns)
1886 G07
1886 G08
Gain Bandwidth vs Supply Voltage
800 TA = 25C AV = -10 700 RL = 1k
10 100
Output Impedance vs Frequency
AV = 100 1
600
RL = 100 RL = 25
500
400
0.1
AV = 10
300 0 2 4 6 8 10 12 TOTAL SUPPLY VOLTAGE (V) 14
0.01 100k
1M 10M FREQUENCY (Hz)
100M
1886 G12
1886 G11
5
LT1886 TYPICAL PERFOR A CE CHARACTERISTICS
Frequency Response vs Supply Voltage, AV = 10
23 22 21 20
GAIN (dB) GAIN (dB)
23
TA = 25C AV = 10 RL = 100
18 17 16 15 14 13 1M VS = 2.5V
VS = 6V
18 17 16 15 14 VS = 2.5V
VS = 6V
GAIN (dB)
19
10M 100M FREQUENCY (Hz)
Frequency Response vs Supply Voltage, AV = -1
3 2 1 0 VS = 2.5V VS = 6V 38 35 32 29
GAIN (dB)
GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 1M TA = 25C AV = -1 RL = 100 RF = RG = 1k RC = 124 CC = 100pF SEE FIGURE 2 10M 100M FREQUENCY (Hz) 1G
1886 G16
26 23 20 17 14 11 8 1M
200pF 100pF 50pF
SLEW RATE (V/s)
Power Supply Rejection vs Frequency
100 90 POWER SUPPLY REJECTION (dB) 80 70 60 50 40 30 20 10 0 100k 1M 10M FREQUENCY (Hz) 100M
1886 G19
COMMON MODE REJECTION RATIO (dB)
80 70 60 50 40 30 20 10 0 100k 1M 10M FREQUENCY (Hz)
OUTPUT TO INPUT CROSSTALK (dB)
(-) SUPPLY
(+) SUPPLY
6
UW
1886 G13
Frequency Response vs Supply Voltage, AV = -10
9 TA = 25C AV = -10 RL = 100 8 7 6 5 4 3 2 1 0 10M 100M FREQUENCY (Hz) 1G
1886 G14
Frequency Response vs Supply Voltage, AV = 2
VS = 2.5V VS = 6V
22 21 20 19
TA = 25C AV = 2 RL = 100 RF = RG = 1k RC = 124 CC = 100pF SEE FIGURE 3 10M 100M FREQUENCY (Hz) 1G
1886 G15
1G
13 1M
-1 1M
Frequency Response vs Capacitive Load
350
Slew Rate vs Temperature
AV = -10 RL = 100 VS = 6V +SR -SR +SR 100 50 0 -50 VS = 2.5V -SR
VS = 6V TA = 25C AV = 10 NO RL
1000pF 500pF
300 250 200 150
10M 100M FREQUENCY (Hz)
1G
1886 G17
-25
0 25 50 75 TEMPERATURE (C)
100
125
1886 G18
Common Mode Rejection Ratio vs Frequency
100 0 VS = 6V TA = 25C -10 -20 -30 -40 -50 -60 -70 -80 -90 90
Amplifier Crosstalk vs Frequency
VS = 6V AV = 10 RL = 100 INPUT = -20dBm
VS = 6V AV = 10
BA
AB
100M
1886 G20
-100 1M
10M 100M FREQUENCY (Hz)
1G
1886 G21
LT1886 TYPICAL PERFOR A CE CHARACTERISTICS
Harmonic Distortion vs Frequency, AV = 10, VS = 6V
0 -10 -20
DISTORTION (dBc)
TA = 25C AV = 10 2VP-P OUT
DISTORTION (dBc)
-40 -50 -60 -70 -80 -90 2nd 3rd RL = 25
2nd 3rd
-40 -50 -60 -70 -80 RL = 25
DISTORTION (dBc)
-30
-100 100k
RL = 100 1M FREQUENCY (Hz) 10M
1886 G22
Harmonic Distortion vs Resistive Load
0 -10 -20 TA = 25C VS = 2.5V AV = 10 2VP-P OUT f = 1MHz 0 -10 -20
DISTORTION (dBc)
DISTORTION (dBc)
-40 -50 -60 -70 -80 -90 3rd 2nd
-40 -50 -60 -70 -80 -90 2nd 3rd 2nd 3rd 0 2 RL = 100 4 6 8 10 OUTPUT VOLTAGE (VP-P) 12
1886 G26
DISTORTION (dBc)
-30
-100 1 10 100 LOAD RESISTANCE () 1k
1886 G25
Harmonic Distortion vs Output Swing, AV = 2, VS = 6V
0 -10 -20 TA = 25C RF = RG = 1k RC = 124 CC = 100pF f = 1MHz SEE FIGURE 3 0 -10 -20
DISTORTION (dBc)
HIGHEST HARMONIC DISTORTION (dBc)
DISTORTION (dBc)
-30 -40 -50 -60 -70 -80 -90
RL = 25 2nd 2nd 3rd 3rd 0 2
RL = 100
-100
4 6 8 10 OUTPUT VOLTAGE (VP-P)
UW
1886 G28
Harmonic Distortion vs Frequency, AV = 10, VS = 2.5V
0 -10 -20 -30 TA = 25C AV = 10 2VP-P OUT
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
Harmonic Distortion vs Resistive Load
TA = 25C VS = 6V AV = 10 2VP-P OUT f = 1MHz
2nd 3rd
2nd 3rd
2nd
-90 -100 100k
3rd
RL = 100 1M FREQUENCY (Hz) 10M
1886 G23
1
10 100 LOAD RESISTANCE ()
1k
1886 G24
Harmonic Distortion vs Output Swing, AV = 10, VS = 6V
0 TA = 25C f = 1MHz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
Harmonic Distortion vs Output Swing, AV = 10, VS = 2.5V
TA = 25C f = 1MHz
-30
RL = 25
RL = 25 2nd 3rd 2nd 3rd 0 1 RL = 100 5
1886 G27
-100
2 3 4 OUTPUT VOLTAGE (VP-P)
Harmonic Distortion vs Output Swing, AV = 2, VS = 2.5V
-30 TA = 25C RF = RG = 1k RC = 124 CC = 100pF f = 1MHz SEE FIGURE 3
Harmonic Distortion vs Output Current, VS = 6V
TA = 25C AV = 10 f = 1MHz RL = 5 -50 RL = 10 -60 RL = 25 -70
-40
-30 -40 -50 -60 -70 -80 -90
RL = 25 2nd 3rd 2nd 3rd 0 1 RL = 100 2 3 4 OUTPUT VOLTAGE (VP-P) 5
1886 G29
-100 12
-80 0 200 300 400 100 PEAK OUTPUT CURRENT (mA) 500
1886 G30
7
LT1886 TYPICAL PERFOR A CE CHARACTERISTICS
Harmonic Distortion vs Output Current, VS = 2.5V
-30 HIGHEST HARMONIC DISTORTION (dBc) OUTPUT VOLTAGE SWING (VP-P) TA = 25C AV = 10 f = 1MHz RL = 5 -50 RL = 10 -60 RL = 25 -70
-40
-80 0 100 150 200 50 PEAK OUTPUT CURRENT (mA) 250
1886 G30
Small-Signal Transient, AV = 10
Large-Signal Transient, AV = 10
8
UW
1886 G33 1886 G36
Undistorted Output Swing vs Frequency
12 10 8 6 4 2 0 100k TA = 25C AV = 10 RL = 100 1% DISTORTION VS = 2.5V VS = 6V
1M FREQUENCY (Hz)
10M
1886 G32
Small-Signal Transient, AV = -10
Small-Signal Transient, AV = 10, CL = 1000pF
1886 G34
1886 G35
Large-Signal Transient, AV = -10
Large-Signal Transient, AV = 10, CL = 1000pF
1886 G37
1886 G38
LT1886
APPLICATIO S I FOR ATIO
Input Considerations The inputs of the LT1886 are an NPN differential pair protected by back-to-back diodes (see the Simplified Schematic). There are no series protection resistors onboard which would degrade the input voltage noise. If the inputs can have a voltage difference of more than 0.7V, the input current should be limited to less than 10mA with external resistance (usually the feedback resistor or source resistor). Each input also has two ESD clamp diodes--one to each supply. If an input drive exceeds the supply, limit the current with an external resistor to less than 10mA. The LT1886 design is a true operational amplifier with high impedance inputs and low input bias currents. The input offset current is a factor of ten lower than the input bias current. To minimize offsets due to input bias currents, match the equivalent DC resistance seen by both inputs. The low input noise current can significantly reduce total noise compared to a current feedback amplifier, especially for higher source resistances. Layout and Passive Components With a gain bandwidth product of 700MHz the LT1886 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and a combination of RF-quality supply bypass capacitors (i.e., 470pF and 0.1F). As the primary applications have high drive current, use low ESR supply bypass capacitors (1F to 10F). For best distortion performance with high drive current a capacitor with the shortest possible trace lengths should be placed between Pins 4 and 8. The optimum location for this capacitor is on the back side of the PC board. The DSL driver demo board (DC304) for this part uses a Taiyo Yuden 10F ceramic (TMK432BJ106MM). The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause frequency peaking. In general, use feedback resistors of 1k or less. Thermal Issues The LT1886 enhanced JA SO-8 package has the V- pin fused to the lead frame. This thermal connection increases
U
the efficiency of the PC board as a heat sink. The PCB material can be very effective at transmitting heat between the pad area attached to the V- pin and a ground or power plane layer. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by the device. Table 1 lists the thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with 2oz copper. This data can be used as a rough guideline in estimating thermal resistance. The thermal resistance for each application will be affected by thermal interactions with other components as well as board size and shape.
Table 1. Fused 8-Lead SO Package
COPPER AREA (2oz) TOPSIDE BACKSIDE 2500 sq. mm 1000 sq. mm 600 sq. mm 180 sq. mm 180 sq. mm 180 sq. mm 180 sq. mm 180 sq. mm 180 sq. mm 2500 sq. mm 2500 sq. mm 2500 sq. mm 2500 sq. mm 1000 sq. mm 600 sq. mm 300 sq. mm 100 sq. mm 0 sq. mm TOTAL COPPER AREA 5000 sq. mm 3500 sq. mm 3100 sq. mm 2680 sq. mm 1180 sq. mm 780 sq. mm 480 sq. mm 280 sq. mm 180 sq. mm JA 80C/W 92C/W 96C/W 98C/W 112C/W 116C/W 118C/W 120C/W 122C/W
W
U
U
Calculating Junction Temperature The junction temperature can be calculated from the equation: TJ = (PD)(JA) + TA TJ = Junction Temperature TA = Ambient Temperature PD = Device Dissipation JA = Thermal Resistance (Junction-to-Ambient) As an example, calculate the junction temperature for the circuit in Figure 1 assuming an 85C ambient temperature. The device dissipation can be found by measuring the supply currents, calculating the total dissipation and then subtracting the dissipation in the load.
9
LT1886
APPLICATIO S I FOR ATIO
6V
+ -
909 100 50 1K 100 -4V f = 1MHz 4V
-6V
Figure 1. Thermal Calculation Example
The dissipation for the amplifiers is: PD = (63.5mA)(12V) - (4V/2)2/(50) = 0.6W The total package power dissipation is 0.6W. When a 2500 sq. mm PC board with 2oz copper on top and bottom is used, the thermal resistance is 80C/W. The junction temperature TJ is: TJ = (0.6W)(80C/W) + 85C = 133C The maximum junction temperature for the LT1886 is 150C so the heat sinking capability of the board is adequate for the application. If the copper area on the PC board is reduced to 180 sq. mm the thermal resistance increases to 122C/W and the junction temperature becomes: TJ = (0.6W)(122C/W) + 85C = 158C which is above the maximum junction temperature indicating that the heat sinking capability of the board is inadequate and should be increased. Capacitive Loading The LT1886 is stable with a 1000pF capacitive load. The photo of the small-signal response with 1000pF load in a gain of 10 shows 50% overshoot. The photo of the largesignal response with a 1000pF load shows that the output slew rate is not limited by the short-circuit current. The
Vi RC CC (OPTIONAL)
Figure 2. Compensation for Inverting Gains
Figure 3 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the network is bootstrapped. This network can also be placed between the inverting input and an AC ground. Another compensation scheme for noninverting circuits is shown in Figure 4. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of
10
+
-
U
Typical Performance Curve of Frequency Response vs Capacitive Load shows the peaking for various capacitive loads. This stability is useful in the case of directly driving a coaxial cable or twisted pair that is inadvertently unterminated. For best pulse fidelity, however, a termination resistor of value equal to the characteristic impedance of the cable or twisted pair (i.e., 50/75/100/135) should be placed in series with the output. The other end of the cable or twisted pair should be terminated with the same value resistor to ground. Compensation
1886 F01
W
U
U
+
-
The LT1886 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. Figure 2 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by RC and CC should be less than 15MHz to minimize peaking. The Typical Curve of Frequency Response vs Supply Voltage, AV = -1 shows less than 1dB of peaking for a break frequency of 12.8MHz.
RF RG Vo Vi Vo = -RF RG
(RC || RG) RF/9 1 2RCCC
1886 F02
< 15MHz
LT1886
APPLICATIO S I FOR ATIO
Figures 3 and 4 can be combined as shown in Figure 5. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies.
Vo Vi RC CC (OPTIONAL) =1+ RF RG
Vi Vo
(RC || RG) RF/9 1 < 15MHz
RF RG
2RCCC
Figure 3. Compensation for Noninverting Gains
Vo Vi
= 1 (LOW FREQUENCIES) =1+ RF RG (HIGH FREQUENCIES)
Vi VO
RF RG CC
RG RF/9 1 2RGCC < 15MHz
Figure 4. Alternate Noninverting Compensation
Vi
RC CC
Vo
RF RG CBIG
Vo Vi
= 1 AT LOW FREQUENCIES =1+ RF RG =1+ RF (RC || RG) AT HIGH FREQUENCIES
1886 F05
RG
AT MEDIUM FREQUENCIES
Figure 5. Combination Compensation
Output Loading The LT1886 output stage is very wide bandwidth and able to source and sink large currents. Reactive loading, even isolated with a back-termination resistor, can cause ringing at frequencies of hundreds of MHz. For this reason, any design should be evaluated over a wide range of output conditions. To reduce the effects of reactive loading, an optional snubber network consisting of a series RC across the load can provide a resistive load at high frequency. Another option is to filter the drive to the load. If a back-
An alternate method of back-termination is shown in Figure 7. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor of n. To analyze this circuit, first ground the input. As RBT = RL/n, and assuming RP2>>RL we require that: Va = Vo (1 - 1/n) to increase the effective value of RBT by n. Vp = Vo (1 - 1/n)/(1 + RF/RG) Vo = Vp (1 + RP2/RP1) Eliminating Vp, we get the following: (1 + RP2/RP1) = (1 + RF/RG)/(1 - 1/n)
-
Vi
+
U
termination resistor is used, a capacitor to ground at the load can eliminate ringing. Line Driving Back-Termination The standard method of cable or line back-termination is shown in Figure 6. The cable/line is terminated in its characteristic impedance (50, 75, 100, 135, etc.). A back-termination resistor also equal to to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage.
CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL RBT VO RL RF RBT = RL Vo Vi = 1 2 (1 + RF/RG)
1886 F06
W
U
-
+
U
1886 F03
-
+
-
+
1886 F04
Figure 6. Standard Cable/Line Back-Termination
11
LT1886
APPLICATIO S I FOR ATIO
For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 = 12.3. Note that the overall gain is increased:
RP2 / (RP2 + RP1) Vo = Vi (1+ 1/ n) / (1+ RF / RG ) - RP1 / (RP2 + RP1)
[
][
A simpler method of using positive feedback to reduce the back-termination is shown in Figure 8. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of -RF/RP from -Vo to Va Va = Vo (RF/RP) and assuming RP >> RL, we require Va = Vo (1 - 1/n) solving RF/RP = 1 - 1/n So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: Vo/Vi = (1 + RF/RG + RF/RP)/[2(1 - RF/RP)] ADSL Driver Requirements The LT1886 is an ideal choice for ADSL upstream (CPE) modems. The key advantages are: 200mA output drive
RP2 RP1 Vi VP
Va RBT RL RF
Vo
1886 F07
RG
FOR RBT = 1+ RF
RL n RP1 RP1 + RP2
( )(
RG Vo Vi =
)
=1-
RG
-Vi
Figure 7. Back-Termination Using Positive Feedback
Figure 8. Back-Termination Using Differential Positive Feedback
12
+
()
1+ RF
1 + 1/n
-
RP1 RP2 + RP1
-
RP2/(RP2 + RP1)
U
with only 1.7V worst-case total supply voltage headroom, high bandwidth, which helps achieve low distortion, low quiescent supply current of 7mA per amplifier and a space-saving, thermally enhanced SO-8 package. An ADSL remote terminal driver must deliver an average power of 13dBm (20mW) into a 100 line. This corresponds to 1.41VRMS into the line. The DMT-ADSL peak-toaverage ratio of 5.33 implies voltage peaks of 7.53V into the line. Using a differential drive configuration and transformer coupling with standard back-termination, a transformer ratio of 1:2 is well suited. This is shown on the front page of this data sheet along with the distortion performance vs line voltage at 200kHz, which is beyond ADSL requirements. Note that the distortion is better than -73dBc for all swings up to 16VP-P into the line. The gain of this circuit from the differential inputs to the line voltage is 10. Lower gains are easy to implement using the compensation techniques of Figure 5. Table 2 shows the drive requirements for this standard circuit. The above design is an excellent choice for desktop applications and draws typically 550mW of power. For portable applications, power savings can be achieved by reducing the back-termination resistor using positive feedback as shown in Figure 9. The overall gain of this circuit is also 10, but the power consumption has been reduced to 350mW, a savings of 36% over the previous design. Note that the reduction of the back-termination resistor has allowed use of a 1:1 transformer ratio.
W
U
U
]
Vi
+ -
RF RG RP
-
+
Va RBT Vo FOR RBT = n= 1- 1 RF RP RF RL Vo Vi RBT -Va -Vo = 1+ RF RG + RF RF RP RL n
RL RP
1 n
RG
2 1-
()
RP
1886 F08
LT1886
APPLICATIO S I FOR ATIO
Table 2. ADSL Upstream Driver Designs
STANDARD Line Impedance Line Power Peak-to-Average Ratio Transformer Turns Ratio Reflected Impedance Back-Termination Resistors Transformer Insertion Loss Average Amplifier Swing Average Amplifier Current Peak Amplifier Swing Peak Amplifier Current Total Average Power Consumption Supply Voltage 100 13dBm 5.33 2 25 12.5 1dB 0.79VRMS 31.7mARMS 4.21V Peak 169mA Peak 550mW Single 12V LOW POWER 100 13dBm 5.33 1 100 8.35 0.5dB 0.87VRMS 15mARMS 4.65V Peak 80mA Peak 350mW Single 12V
Table 2 compares the two approaches. It may seem that the low power design is a clear choice, but there are further system issues to consider. In addition to driving the line, the amplifiers provide back-termination for signals that are received simultaneously from the line. In order to reject the drive signal, a receiver circuit is used such as shown in Figure 10. Taking advantage of the differential nature of the signals, the receiver can subtract out the drive signal and amplify the received signal. This method works well for standard back-termination. If the backtermination resistors are reduced by positive feedback, a portion of the received signal also appears at the amplifier outputs. The result is that the received signal is attenuated
Vi
+ -
1k 523
8.45
1.21k
1:1
1F
523 1k
1.21k
AV = 10 8.45
-
LT1813
-Vi
RF
1886 F09
Figure 9. Power Saving ADSL Modem Driver
Figure 10. Receiver Configuration
+
-
U
by the same amount as the reduction in the back-termination resistor. Taking into account the different transformer turns ratios, the received signal of the low power design will be one third of the standard design received signal. The reduced signal has system implications for the sensitivity of the receiver. The power reduction may, or may not, be an acceptable system tradeoff for a given design. Demo Board Demo board DC304 has been created to provide a versatile platform for a line driver/receiver design. (Figure 11 shows a complete schematic.) The board is set up for either single or dual supply designs with Jumpers 1-4. The LT1886 is set up for differential, noninverting gain of 3. Each amp is configured as in Figure 5 for maximum flexibility. The amplifiers drive a 1:2 transformer through back-termination resistors that can be reduced with optional positive feedback. The secondary of the transformer can be isolated from the primary with Jumper 5. A differential receiver is included using the LT1813, a dual 100MHz, 750V/s operational amplifier. The receiver gain from the transformer secondary is 2, and the drive signals are rejected by approximately a factor of 14dB. Other optional components include filter capacitors and an RC snubber network at the transformer primary.
Va RBT VL 1:n RL -Va RBT -VL RF RD RG RL n2
W
U
U
-
+
100
= REFLECTED IMPEDANCE RL 2n2
LT1813
+
VRX VBIAS RL
= ATTENUATION OF Va
2n2
+ RBT RL
+
-
RD RG
SET
RG RD
=
2n2 RL 2n2 + RBT
1886 F10
13
LT1886
APPLICATIO S I FOR ATIO
C1 0.1F JP1
+DRV V R1 10k C3 1F
+
R3 20k JP3
R20 130 C19 100pF R6 499 C4 1F C5 1F R8 499
R2 10k V-
-DRV
JP2 C2 0.1F C10 470pF C11 0.1F
-RCV 1
V+
V+
C14 10F GND C16 10F V-
+
C15 1F
C18 10F
+RCV 7
+
C17 1F
JP4 C13 0.1F
Figure 11. LT1886, LT1813 DSL Demo Board (DC304)
14
+
5
-
R4 20k
C20 100pF R4 130
U
V+ C8 0.1F 3 C9 470pF TP1 TP2 R9 12.4 C21 470pF TP5 6 9 LINE OUT 7 10 R7 12.4 TP3 7 R10 12.4 C22 470pF C6 10pF TP4 C23 470pF 2 JP5 4 TP6
W
U
U
+ -
8 LT1886 1 R5 1k R18
2
R19 6 R7 1k LT1886 4
SEPARATE SECONDARY GROUND
COILCRAFT X8390-A OR EQUIVALENT
V+ C12 0.1F
R11 4.02k
R12 2k
8
-
LT1813
2
R13 1k
+
3
+
LT1813
5 R15 2k
-
4 V-
6
R14 4.02k
R16 1k
C7 10pF
1886 F11
LT1886
SI PLIFIED SCHE ATIC
V+ I4 Q3 Q4 Q5 OUT Q6 D1 -IN Q1 Q2 C1 +IN Q7 Q9 Q8
PACKAGE DESCRIPTIO
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 (0.406 - 1.270)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
W
W
D2
I1 V-
I2
I3
1886 SS
Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1
2
3
4
0.053 - 0.069 (1.346 - 1.752)
0.004 - 0.010 (0.101 - 0.254)
0.050 (1.270) BSC
SO8 1298
15
LT1886
TYPICAL APPLICATIO
Considerations for Fault Protection The basic line driver design presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current, 500mA or more, to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. If left unchecked, the high DC current can heat the LT1886 to destruction. Using DC blocking capacitors to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission.
5V 3 130 2 100pF
+ -
8 1 6.19
1/2 LT1886
1k 866 2k 1:2*
+
VIN
-
100pF
866 1k 6 130 5
1/2 LT1886
7
4 -5V
RELATED PARTS
PART NUMBER LT1207 LT1361 LT1396 LT1497 LT1795 LT1813 DESCRIPTION Dual 250mA, 60MHz Current Feedback Amplifier Dual 50MHz, 800V/s Op Amp Dual 400MHz, 800V/s Current Feedback Amplifier Dual 125mA, 50MHz Current Feedback Amplifier Dual 500mA, 50MHz Current Feedback Amplifier Dual 100MHz, 750V/s, 8nV/Hz Op Amp COMMENTS Shutdown/Current Set Function 15V Operation, 1mV VOS, 1A IB 4.6mA Supply Current Set, 80mA IOUT 900V/s Slew Rate Shutdown/Current Set Function, ADSL CO Driver Low Noise, Low Power Differential Receiver
1886fa LT/LCG 0301 2K REV A * PRINTED IN USA
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbsTM, varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT1886 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs.
TransZorb is a registered trademark of General Instruments, GSI
Split Supply 5V ADSL CPE Line Driver
5V 0.47F** BAV99** -5V
VL
=5
(ASSUME 0.5dB TRANSFORMER POWER LOSS)
+
100 VL
VIN REFLECTED LINE IMPEDANCE = 100 / 22 = 25 EFFECTIVE TERMINATION = 2 * 6.19 * 2k 1k EACH AMPLIFIER: 0.56VRMS, 29.9mARMS 3V PEAK, 160mA PEAK = 24.8
2k
-
+
-
6.19 5V 0.47F** BAV99** -5V 1886 TA02
*COILCRAFT X8390-A OR EQUIVALENT **SEE TEXT REGARDING FAULT PROTECTION
(c) LINEAR TECHNOLOGY CORPORATION 1999

▲Up To Search▲

Price & Availability of LT1886

	To Download LT1886 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .